Capacitors are critical components of analog integrated circuit devices and memory devices. They are also used in many mixed signal or high frequency applications requiring both high performance and high speed. Low series resistance, low loss, high Q and low (RC) time constants are required in these high frequency applications for high performance. Metal-insulator-metal (MIM) capacitors are commonly used, such as in high performance applications.
MIM capacitors typically include metal electrodes separated by a dielectric. The MIM structure and materials frequently and advantageously allow integration of its fabrication with the damascene interconnect process. In conventional methods, the electrodes are made from Al, Cu, or alloys thereof. The thin insulating dielectric layer is usually made from silicon oxide or silicon nitride deposited by chemical vapor deposition (CVD). MIM capacitors offer a number of advantages providing a relatively constant value of capacitance over a relatively wide range of voltages. Conventional MIM capacitors have a relatively small parasitic resistance, however, they also have a number of disadvantages.
Advanced technology applications frequently require a capacitance in excess of 100 nF. Even with an ultra thin gate oxide, high capacitance requires a large silicon area, thereby increasing die size as well as chip and assembly cost. Ultra thin oxides also lead to unacceptably high leakage currents in integrated circuits (e.g. 100 mA for 0.1 mm2 of 12 Å gate oxide). These factors cause problems with power and thermal management, they shorten battery life for mobile applications, and they increase overall cost.
Current MIM capacitor manufacturing methods require a number of photo-lithographic steps to form electrodes and dielectric layers. Since the cross-sectional area of the capacitor plug is small and the difference in height between damascene and capacitor plugs may be great, etching is very difficult to control. If the capacitor metal electrode layers and its dielectric layer are formed on an entire layer during fabrication, production costs are very high. When etching to form the electrodes and dielectric layer, it is very easy to cause damage on the edge portion of the metal capacitor.
The following references provide additional background. In U.S. Pat. No. 6,680,542, Gibson et al. show a metal-on-metal capacitor structure and process and an associated damascene process. In U.S. Pat. No. 6,358,792, Hsue et al. show a method for fabricating a lower capacitor electrode concurrently with an interconnect metal. In U.S. Pat. No. 6,140,693, Weng et al. show a metal capacitor for ultra large-scale integration (ULSI) compatible with the damascene process. In U.S. Pat. No. 6,069,051, Nguyen et al. show a method of fabricating metal-to-metal capacitors using planar processing compatible with the damascene process. In U.S. Pat. No. 6,492,226, Hsue et al. show a method for forming a metal capacitor in a damascene process. In U.S. Pat. No. 6,559,493, Lee et al. show an improved stacked MIM capacitor. In U.S. Pat. No. 6,436,787, Shih et al. show a method for forming a crown MIM capacitor integrated with the damascene process. In U.S. Pat. Pub. No. 2004/0201057, Lien et al. show a method for forming a MIM capacitor in a copper damascene process. However, none of these references describes the novel structure and method of this invention that provides for the integration of specific elements of a MIM capacitor into a damascene fabrication process.